1. Field of the Invention
The present invention relates to a method of forming interconnects and contacts between elements in a semiconductor or integrated circuit, as well as a device or integrated circuit having these interconnects and contacts.
2. Discussion of the Background
A variety of methods have been used to make electrical connections between transistors in integrated circuit devices. One method makes use of self-aligned contacts (SAC), or SAC technology, and is illustrated in FIGS. 1a-1c. SAC technology allows contacts to be made to portions of the substrate, typically the source or drain of a transistor element, which can overlap the gate of a transistor, or overlap the edge of diffusion, without making electrical contact with these overlapped areas. FIG. 1a shows gates 12 encapsulated with a cap 14 and spacers 16. Typically, the gate 12 is made of highly doped polysilicon, and the caps 14 and spacers 16 are made from an insulator, such as silicon oxide. These are present on the substrate 10, and these elements are isolated from other regions of the semiconductor substrate by isolation region 18, typically made as an oxidized portion of the substrate. The encapsulated gate is typically made by depositing a layer of polysilicon, and depositing a layer of oxide on the polysilicon layer. This is then followed by a mask and etch of the oxide and polysilicon together. The spacers 16 may be formed by (a) an anisotropic etch of the oxide deposited on the gate or by (b) spacer oxide deposition, followed by spacer etch.
FIG. 1b shows the next step in formation of the self-aligned contacts. A SAC etch stop layer 20, typically about 700 .ANG. of silicon nitride, is deposited on the substrate 10, and on the gates 12, the caps 14 and spacers 16. A thick dielectric layer 24 is applied over the etch stop layer 20. The dielectric layer is typically made of doped silicon dioxide (e.g., spin-on glass, BPSG, reflow). The dielectric layer 24 is then planarized, for example using chemical-mechanical polishing (CMP).
FIG. 1c shows the final SAC structure. Vias are formed in the dielectric layer 24 by a series of masking and etching steps. The etching proceeds quickly through the dielectric 24 until it reaches the etch stop layer 20, where the etching rate is greatly reduced. Thus, if the masking and etching is somewhat misaligned from the substrate contact regions 22 (i.e., source or drain), SAC technology prevents misalignment of the via, because the etch stop layer greatly slows the vertical etching process, preventing the via from penetrating through caps 14 to the gates 12. The etch chemistry is then changed to selectively remove the exposed portions of the etch stop layer 20. Once the vias are formed, they are filled with a conductor, such as tungsten, to form metal contacts 32. After planarizing the metal contact 32 to the surface of the dielectric layer 24, the contacts can be connected to each other and/or to other circuit components with surface metal interconnects 30. A distinct advantage of SAC technology is that the contacts generally cannot be misaligned, allowing various circuit components to be placed very close together.
A different method has been used for making electrical contact between two closely spaced regions or elements of a semiconductor circuit (i.e., local interconnects) illustrated in FIGS. 2a-2c. FIG. 2a, which is identical to FIG. 1a, or a side or edge-on view of a device, illustrating gates 12, which are encapsulated with caps 14 and spacers 16, on substrate 10. Also present is isolation region 18. A dielectric layer 24 is then added, and planarized, as illustrated in FIG. 2b. When forming a local interconnect, the dielectric layer 24 has a thickness at this stage which corresponds to the final thickness of the local interconnect, typically 2000 .ANG..
FIG. 2c shows the final structure including the local interconnect 34. The local interconnect 34 is prepared by masking and etching a trough (generally rectangularly-shaped when viewed from the top) in the dielectric 24 without etching through the caps 14 over the gates 12. The dielectric layer 24 is etched through to the substrate contact regions 22. The trough is then filled with a conductor, such as tungsten, and planarized to the level of the dielectric 24, thereby forming an electrical connection between the substrate regions 22.
The process of forming a trough in a dielectric layer and then filling the trough with a conductor is also known as a metal damascene process. Typically, the normal damascene process is used only for local interconnects, as the interconnects tend to be shallow, and therefore have a high resistance. The local interconnects are only suitable for providing an electrical connection over short distances, because of their high resistance.
SAC technology is typically used to form metal contacts from substrate contact regions, through a dielectric layer, to form electrical contacts with the surface metal interconnects between circuit elements. SAC technology, together with the surface metal interconnects, allows long range contacts to be formed between substrate contact regions, and hence a variety of circuit elements, across the semiconductor device.
Metal interconnects running along the surface of the dielectric layer are useful for long range contacts, regardless of whether SAC technology or a metal damascene process is used. These metal contacts are separately deposited, masked and etched, and planarized, requiring additional steps.
The present invention combines aspects of both damascene and SAC technologies, providing robust, low resistance connections and contacts between substrate contact regions across a semiconductor device, removing or reducing the need for metal interconnects on the dielectric layer.